45nm

[Jonathan]

http://www.edn.com/index.asp?layout=blo ... 1870017387

Blog (professional, journalisty blog, but blog) with popups and ads. Still an interesting interview with Intel's process folks.

[quantus]

Third, as we have previously speculated, is that Intel is in a position to impose restrictive design rules on their design teams. This creates another degree of freedom for the lithographers, permitting them to simply ban patterns that give the dry lithography trouble.

That helps a lot.

[Jonathan]

I don't get it. Why don't the foundries tell their customers to suck it up?

[quantus]

Designers are cry babies? Seriously thought, you're right, fabs could force this on designers, and they do to some extent when absolutely required. It makes design a bit more of a pain though because there are now more rules to check and area usage isn't as good negating some of the shrink benefit. Really, the problem stems from the fact that I might say, extend the line by x past a via to avoid litho pullback and they will do it to pass DRC. But, they might do it at 90 degrees to the main line creating a dog leg which actually ends up making the OPC situation worse rather than better. You might say, write a better DRC to avoid dog legs, and I say, "yes sir, right away sir", only to have the designers go off and find even more obscure ways to push the letter of rules around the intent. (Think of what we did in 322 and 525 to save area!) In the end, you just wind up with longer DRC runs for the trouble.