Mohtalim

http://www.eet.com/news/latest/showArti ... =193005741

Jonathan should try to join a group working on chips for this research.

It's not... unattractive.

Each tile includes a small core, or compute element, with a simple instruction set for processing floating-point data, but is not Intel x86-based processor compatible.

Definitely is research, though. I'm not really sure why they taped something out, other than for Justin Rattner to have something to wave around.

Slapping down 80 FPUs on a die isn't hard, actually. Doing the interconnect is slightly more difficult, but the actually interesting problem is the programming model.

Maybe it's easier to play around with a real live chip with a programmable routing mesh? That'd be my guess. It'd be a pain to model 80 processors and then have to deal with the routing mesh as well. It'd suck though if they messed up the cache coherency protocol though. That wafer'd be pretty worthless if they did. Heh, I bet Vinny remembers trying to model just a couple of processors to be cache coherent... They've got 80. Also, I think there was a problem of knowing how many processors is the minimum you need to model you coherency protocol with in order to verify its total correctness for any number of processors.

Wow, that's digging up the past. For some reason I think only three processors are needed with a protocol that takes advantage of waitfree synchronization, but I'm probably wrong considering how much I've forgotten.

For an easy/correct answer, just ask Andreas G. Nowatzyk.

I believe it was 5 for MESI...

Anand wrote:The chip is simply a technology demo and won't be productized in any way.

Which is just a waste. We have better ways to validate performance than taping out a chip, and functional validation is silly for a technology demo.

Here was the actually interesting bit.

http://www.anandtech.com/tradeshows/sho ... i=2841&p=2

Games which require multiple cores are my new sex.