SystemVerilog

[Jonathan]

It's SystemVerilog! It's the Verilog with System in front of it! Is it SystemC? Is it SuperVerilog 2000? Is it some combination of both? I don't know!

Actually, preliminary research indicates this is probably the rebranded Verilog-with-extras that we saw in school, courtesy of Thomas, Don. But that's just a theory based on quick Googling.

[Jonathan]

This document numbers the generations of Verilog as follows:
— “Verilog 1.0” is the IEEE Std. 1364-1995 Verilog standard, which is also called Verilog-1995
— “Verilog 2.0” is the IEEE Std. 1364-2001 Verilog standard, commonly called Verilog-2001; this generation
of Verilog contains the first significant enhancements to Verilog since its release to the public in 1990
— “SystemVerilog 3.x” is Verilog-2001 plus an extensive set of high-level abstraction extensions, as defined
in this document
— SystemVerilog 3.0, approved as an Accellera standard in June 2002, includes enhancements primarily
directed at high-level architectural modeling
— SystemVerilog 3.1, approved as an Accellera standard in May, 2003, includes enhancements primarily
directed at advanced verification and C language integration
The Accellera initiative to extend Verilog is an ongoing effort under the direction of the Accellera HDL+ Technical
Subcommittee. This committee will continue to define additional enhancements to Verilog beyond SystemVerilog
3.1.
SystemVerilog is built on top of Verilog 2001. SystemVerilog improves the productivity, readability, and reusability
of Verilog based code. The language enhancements in SystemVerilog provide more concise hardware
descriptions, while still providing an easy route with existing tools into current hardware implementation
flows.

So I think Verilog 1995 is what we used, Verilog 2001 is what they showed us, and Accellera is all like "oooh, buy our Verilog, the Verilog with System in front of it!"